In the manufacture of integrated circuits, a plurality of circuit elements are formed in a monolithic semiconductive chip or structure and interconnected appropriately to provide a desired circuit function. In such integrated circuits, it is often necessary to electrically isolate individual circuit elements from one another. Various techniques are known for providing such isolation including PN junction isolation and dielectric isolation. In one form of dielectric isolation, one or more circuit elements to be isolated from other circuit elements are formed in a mesa that rises above the surrounding portion of the chip so that circuit elements in the top surface of the mesa are isolated both electrically and thermally in a lateral direction from the circuit elements at the top surface of the surrounding portion of the chip. Additionally, vertical isolation can be provided by including a high resistivity region in the mesa.
However, techniques of this kind that use mesas that rise above the plane of the top surface of the bulk of the chip have not found significant use in integrated circuits probably because of the disadvantages of either the need to form the mesas or the resulting non-planarity of the top surface.
For integrated circuit use, it is desirable to have a semiconductive chip or structure which has an essentially planar surface but in which exists one or more regions which provide the isolation of a mesa.